SkyWater SKY130 — MOSFET Device Reference

SKY130 is a mature 130nm bulk CMOS process from SkyWater Technology Foundry, open-sourced in collaboration with Google and eFabless. It is the most widely used open-source PDK in the world, supporting the Efabless/Caravel shuttle program. The process offers 1.8V and 5V/10.5V MOSFET families, MiM caps, poly resistors, MOS varactors, BJTs, and a rich set of RF passives — all under Apache 2.0. PDK documentation: skywater-pdk.readthedocs.io

Technology node 130nm bulk CMOS

LV supply 1.8V (nfet/pfet_01v8)

HV supply 5V gate / 10.5V drain

SPICE model BSIM4 (level=54), subcircuits

Metal stack LI + M1–M5 (6 routing layers)

License Apache 2.0

Device Catalogue — 7 MOSFET Variants in This Dataset

nfet_01v8 (SVT) NMOS · 1.8V · SVT

Standard-Vt NMOS — the workhorse device for all LV analog and mixed-signal design on SKY130. BSIM4 subcircuit model. Can be instantiated with or without the deep N-well (DNW) isolation under the p-well. DNW adds a fourth terminal for body biasing (useful for Vth tuning and substrate noise isolation in analog). Vth₀ ≈ 0.49–0.50V depending on L/W bin. Lmin = 0.15µm.

Vdd nom

1.8 V

Vth₀ (EDR NOM, W/L=7/8)

0.541 V

Lmin drawn

0.15 µm

Wmin drawn

0.42 µm

Vbs range

+0.3 to −1.95 V

Model type

BSIM4 subcircuit

nfet_01v8_lvt (LVT) NMOS · 1.8V · LVT

Low-Vt NMOS. Identical cross-section to nfet_01v8 except for a Vth-adjust implant that lowers threshold voltage. Results in higher on-current for the same overdrive, making it the preferred device for high-speed analog paths (fast OTA input pairs, low-noise LNAs, VCO switching stages) and near-Vt digital. Higher leakage than SVT. Lmin = 0.15µm.

Vth₀ (sim, TT, L range)

~0.43–0.55 V

ΔVth vs SVT

~−600 to −700 mV

Lmin drawn

0.15 µm

Key use case

Fast analog / RF input

Leakage vs SVT

Higher (~2–5×)

DNW option

Yes

pfet_01v8 (SVT) PMOS · 1.8V · SVT

Standard-Vt PMOS, complementary to nfet_01v8. Sits in an N-well as standard. Has lower hole mobility than NMOS (inherent to p-channel physics), so requires larger W to match drive current. |Vth₀| ≈ 0.91–1.0V (varies with L, TT corner). Used for PMOS current mirrors, cascode loads, differential pair tails, and any block requiring a complementary p-channel. BSIM4 subcircuit model, N-well to P-substrate diodes built in.

Vdd nom

1.8 V

|Vth₀| (sim, long-L)

~0.91–1.00 V

Lmin drawn

0.15 µm

Wmin drawn

0.42 µm

Vbs range

−0.1 to +1.95 V

Mobility vs NMOS

Lower (p-channel physics)

pfet_01v8_lvt (LVT) PMOS · 1.8V · LVT

Low-Vt PMOS with Vth-adjust implant for reduced |Vth|. Cross-section identical to SVT pfet_01v8. Preferred in low-headroom PMOS differential pairs (telescopic cascode amplifiers where PMOS has restricted Vgs headroom) and rail-to-rail OTA input stages. Also used in bandgap self-biased current mirrors where faster settling is needed. Higher leakage than SVT PMOS.

|Vth₀| (sim, TT)

~0.17–0.33 V

ΔVth vs SVT (L-dep)

−80 to −200 mV

Lmin drawn

0.15 µm

Leakage vs SVT

Higher

Key use case

Low-headroom analog

DNW option

N-well standard

pfet_01v8_hvt (HVT) PMOS · 1.8V · HVT

High-Vt PMOS — the only HVT device in this dataset (no HVT NMOS is offered in SKY130). Vth-adjust implant raises |Vth| to reduce leakage. Used for ultra-low-leakage load transistors, sleep-mode power gating PMOS switches, and precision current sources where subthreshold leakage must be minimised. Lower drive current than SVT for the same geometry. Important for near-threshold / sub-threshold analog design.

|Vth₀| (sim, TT)

~0.98–1.05 V

ΔVth vs SVT

+130 to +150 mV

Lmin drawn

0.15 µm

Leakage vs SVT

Lower (~10–50×)

Key use case

Power gating / IoT

HVT NMOS?

Not available in SKY130

nfet_g5v0d10v5 NMOS · 5V gate / 10.5V drain

High-voltage NMOS with 5.0V gate oxide and 10.5V drain breakdown. This is a DMOS-type extended-drain device, also called the "HV NMOS." The gate is rated to 5.5V (SPICE valid to 5.5V); the drain can withstand up to 10.5V by design rule (SPICE model valid to 11.0V). Used for power management (LDO pass transistors, DC-DC switches), gate drivers, level shifters, and any block interfacing between the 1.8V digital core and a higher-voltage supply. Lmin = 0.5µm. Vth₀ ≈ 0.78–0.85V.

Vgs max (SPICE valid)

5.5 V

Vds max

10.5 V

Vth₀ (sim, TT)

~0.77–0.79 V

Lmin drawn

0.5 µm

Vbs range

0 to −5.5 V

Key use case

Power mgmt / LDO / gate driver

pfet_g5v0d10v5 PMOS · 5V gate / 10.5V drain

High-voltage PMOS complementary to nfet_g5v0d10v5. Extended-drain PMOS with 5V gate and 10.5V drain. Used in high-side power switches (P-channel MOSFET switches for load control), LDO PMOS pass elements, charge pump drivers, and MV-to-LV level converters. The HV PMOS has notably lower drive current than its NMOS counterpart due to lower hole mobility — size accordingly (typically 3–4× W for equivalent current). Lmin = 0.5µm.

Vgs max (SPICE valid)

−5.5 V

Vds max

−10.5 V

|Vth₀| (sim, TT)

~0.80–0.94 V

Lmin drawn

0.5 µm

Key use case

High-side switch / LDO pass

HV family

g5v0d10v5

Understanding LVT / SVT / HVT in SKY130

🔵 Vt Flavours — Same Gate Oxide, Different Implants

In SKY130, all three 1.8V MOSFET flavours share the same gate oxide (NMOS tox ≈ 4.15nm, PMOS toxm ≈ 4.23nm — slightly different due to process). The threshold voltage is adjusted by varying the channel ion implant dose — a "Vt-adjust implant" layer that shifts the flat-band voltage and hence Vth:

LVT (Low-Vt): reduced channel doping → lower Vth (~0.43–0.55V NMOS, ~0.17–0.33V PMOS). Higher Idsat for same W/L, but higher subthreshold leakage. Best for high-speed analog input pairs or where overdrive headroom is tight at 1.8V supply.

SVT (Standard-Vt): baseline process implant → Vth ~0.53–0.71V NMOS (varies with L), ~0.91–1.0V PMOS. Balanced leakage/performance tradeoff. The default choice for most analog blocks.

HVT (High-Vt): PMOS only in SKY130 — increased channel doping → |Vth| ~0.98–1.05V. Much lower leakage, lower drive current. Used in power gating, IoT near-threshold circuits, and precision bias generators where thermal leakage matters.

Note: nfet_01v8_hvt does not exist in SKY130 — only pfet_01v8_hvt. If you need low-leakage NMOS, you use the SVT device at long L.

⚠ HV Devices: nfet/pfet_g5v0d10v5 — Extended Drain, Not Standard MOSFET

The g5v0d10v5 family is a drain-extended (DMOS-style) device, not a simple thick-oxide gate version of the 1.8V FET. The "g5v0" means 5V gate rating; "d10v5" means 10.5V drain rating. The higher drain voltage is achieved through a lightly-doped extended drain region that drops most of the Vds across a drift region, keeping the high electric field away from the gate oxide. Implications for gm/ID methodology: gm/ID curves will look different from the 1.8V family — lower peak gm/ID (worse intrinsic efficiency), higher Vth, and the fT curves drop off much earlier due to the larger parasitic drain capacitance. Use these only when your supply exceeds ~2.5V or when HV isolation is needed; otherwise the 1.8V SVT device gives far better analog performance per unit current.

Process Corner Guide (from SKY130 PDK)

Typical–Typical. Nominal process. Best estimate of median silicon.

Fast NMOS + Fast PMOS. Low Vth, high drive. Max speed, max dynamic power.

Slow N + Slow P. High Vth, worst-case delay. Max leakage due to EDP tradeoff.

Fast NMOS + Slow PMOS. N–P mismatch. Static noise margin worst case.

Slow NMOS + Fast PMOS. Opposite mismatch. Tests latch-up and pass-gate.

leak

Leakage corner — maximises subthreshold and gate leakage. Critical for IoT standby power budgets.

wafer

Within-wafer variation model — not a standard simulation corner file like tt/ss/ff. Used for advanced variation analysis only.

SKY130 ships corner files: tt, ss, ff, sf, fs, leak (standard simulation corners). "wafer" is a within-wafer variation model, not a standard .lib corner — plus separate Monte Carlo mismatch models (global + local) for all devices. Corner files located at skywater-pdk-libs-sky130_fd_pr/models/sky130.lib.spice.

Key Electrical Parameters — From PDK Model Extraction & Documentation

nfet_01v8 (SVT) — 1.8V NMOS, TT corner, 25°C

Parameter	SS	TT	FF	Unit
Vth (EDR W/L=7/8, long-L)	—	0.541	—	V
Vth (EDR W/L=7/8)	0.557	—	0.520	V
Vth (EDR W/L=7/0.15, short-L)	—	0.700	—	V
Vth (EDR W/L=7/0.15)	0.739	—	0.661	V
SubVt slope (typical)	—	~80–90	—	mV/dec
Ioff @ Vds=1.8V, 25°C	—	<1	—	pA/µm
Max Vgs	1.95 V absolute			V

nfet_01v8_lvt (LVT) — 1.8V Low-Vt NMOS

Parameter	SS	TT	FF	Unit
Vth₀ (sim, TT, L=0.15–3µm)	—	~0.43–0.55	—	V
ΔVth vs SVT (sim-derived)	~−600 to −700 mV			V
SubVt slope	—	~75–85	—	mV/dec
Ioff @ Vds=1.8V, 25°C	—	~2–5×	—	× SVT
gm/ID advantage @ same Vov	~Same; higher ID/W at same Vov			—

pfet_01v8 (SVT) — 1.8V PMOS, TT corner, 25°C

Parameter	SS	TT	FF	Unit
\|Vth\| (EDR W/L=7/0.15, short-L)	—	0.781	—	V
\|Vth\| (EDR W/L=7/0.15)	0.858	—	0.705	V
\|Vth\| (EDR W/L=7/8, long-L)	—	1.050	—	V
SubVt slope	—	~80–95	—	mV/dec
PMOS mobility vs NMOS	Lower (p-channel physics)			—
Max \|Vgs\|	1.95 V absolute			V

pfet_01v8_hvt (HVT) — 1.8V High-Vt PMOS

Parameter	SS	TT	FF	Unit
\|Vth₀\| (sim, TT)	—	~0.98–1.05	—	V
Δ\|Vth\| vs SVT	+130 to +150 mV			V
Ioff vs SVT (approx)	10–50× lower leakage			—
Idsat penalty vs SVT	~10–15% lower at same W/L			—
Lmin drawn	0.35 µm			µm

nfet_g5v0d10v5 — 5V/10.5V HV NMOS

Parameter	SS	TT	FF	Unit
Vth₀ (sim, TT, L=0.5µm)	—	~0.78	—	V
Max Vgs	5.0 V			V
Max Vds (drain breakdown)	10.5 V			V
Vbs range	0 to −5.5 V			V
Lmin drawn	0.5 µm			µm
Peak gm/ID vs 1.8V devices	Lower — larger Vth, drift resistance			—

pfet_g5v0d10v5 — 5V/10.5V HV PMOS

Parameter	SS	TT	FF	Unit
\|Vth₀\| (sim, TT)	—	~0.80–0.94	—	V
Max \|Vgs\|	5.0 V			V
Max \|Vds\|	10.5 V			V
Drive current vs HV NMOS	~0.3–0.4× (hole mobility)			—
Recommended W sizing	3–4× NMOS for same current			—

Instance Parameter Limits (Design Constraints)

Device (sky130_fd_pr__)	Type	W min (µm)	L min (µm)	L max (µm)	Vdd nom	Vds abs max	Notes
nfet_01v8	NMOS SVT	0.42	0.15	—	1.8V	1.95V	DNW option available
nfet_01v8_lvt	NMOS LVT	0.42	0.15	—	1.8V	1.95V	DNW option available
pfet_01v8	PMOS SVT	0.42	0.15	—	1.8V	1.95V	Lmin larger than NMOS
pfet_01v8_lvt	PMOS LVT	0.42	0.15	—	1.8V	1.95V	—
pfet_01v8_hvt	PMOS HVT	0.42	0.15	—	1.8V	1.95V	Only HVT device in SKY130
nfet_g5v0d10v5	NMOS HV	0.42	0.5	—	5V gate	10.5V drain	Extended drain DMOS
pfet_g5v0d10v5	PMOS HV	0.42	0.5	—	5V gate	10.5V drain	Extended drain DMOS

* PMOS Lmin is 0.15µm, same as NMOS — confirmed from EDR test geometries (VTXPSN15S uses W/L=0.42/0.15). Earlier incorrect claim of 0.35µm has been removed. Source: skywater-pdk.readthedocs.io/rules/device-details

Designer's Quick Reference

SVT NMOS Vth₀ (TT, sim)

0.53–0.71 V

L=3µm → 0.53V; L=0.15µm → 0.71V

LVT NMOS ΔVth vs SVT

−80 to −200 mV

Varies with L; Vt-adjust implant only

SVT PMOS |Vth₀| (TT, sim)

~0.91–1.00 V

L=0.35µm → 0.91V; L=3µm → 1.00V

HVT PMOS Δ|Vth| vs SVT

~+50 to +80 mV

Only HVT available = PMOS

HV NMOS Vth₀

~0.77–0.79 V

g5v0d10v5, extended drain

SubVt slope (all 1.8V)

75–95 mV/dec

Typical at 25°C

1.8V Vds absolute max

1.95 V

10% above nominal supply

HV drain abs max

10.5 V

g5v0d10v5 family

PMOS Lmin (same as NMOS)

0.15 µm

EDR tests PMOS at W/L=0.42/0.15

BSIM model level

Level 54 (BSIM4)

Subcircuit wrapper

Corners available

TT / SS / FF / SF / FS / leak / wafer

7 corners + Monte Carlo

Gate oxide tox (1.8V)

~4.15 nm

All LVT/SVT/HVT share same tox

📚 Sources: PDK Device Details · google/skywater-pdk · BSIM vth0 values from sky130_fd_pr model files · All Vth values are extracted from simulation data (TT 25°C) at Vds=0.05V. They vary significantly with L due to SCE — values shown are min/max across the L range. Official EDR specs are proprietary. Vgs/Vbs operating range from PDK RST.