ℒ = w₁·((gm/ID − tA)/σA)² + w₂·((gm/gds − tB)/σB)²SG13G2 is IHP Microelectronics' high-performance 130nm BiCMOS technology offering SiGe:C npn-HBT bipolar transistors with fT = 300 GHz and fmax = 500 GHz, alongside a full CMOS module. The PDK is open source under Apache 2.0 and hosted on GitHub. It provides two gate oxide options (1.2V thin-oxide and 3.3V thick-oxide), a 7-layer aluminium back-end, poly resistors, MIM capacitors, and inductors. All characterisation data in this tool was generated with ngspice using the PSP 103 compact MOSFET models at the TT corner, T = 27°C, VDS = VDD/2, W = 2µm.
sg13_lv_nmos_inh). Body tied to most-negative supply in standard use. Gate stack: thin SiO₂ with poly gate.sg13_hv_nmos_inh). Used for ESD protection, power switches, and mixed-voltage interfaces.| Component | Cell Name | Key Specs | Typical Use |
|---|---|---|---|
| Silicided poly R | rsil | R□ = 7 Ω/sq ±10%, TC₁ = 3100 ppm/K | Low-resistance ESD, bias |
| Poly resistor | rppd | R□ = 260 Ω/sq ±10%, TC₁ = 170 ppm/K | General analog, moderate matching |
| Poly resistor high | rhigh | R□ = 1360 Ω/sq ±15%, TC₁ = −2300 ppm/K | High-impedance, bias ladders |
| MIM capacitor | cap_cmim | C' = 1.5 fF/µm² ±10%, V-coeff = −26 ppm/V, TC₁ = 3.6 ppm/K, BV > 15V | Precision analog, bypass, RF |
| MOM capacitor | metal stack | 5 thin metal layers; no primitive; implement manually | RF, high-Q, compact decoupling |
| Inductor | via LVS lib | Spiral inductors; Q and L depend on geometry | LC-VCO, matching networks, RF |
| Layer | Type | Thickness | Sheet R | Notes |
|---|---|---|---|---|
| M1–M5 | Thin Al | ~0.35 µm each | ~75 mΩ/sq | Signal routing, standard interconnect |
| M6 (TopMetal1) | Thick Al | 2 µm | ~10 mΩ/sq | Power, inductors, redistribution |
| M7 (TopMetal2) | Thick Al | 3 µm | ~7 mΩ/sq | Thick power bus, RF ground plane |
| MIM layer | TaN/TiN/Al | — | — | cap_cmim, between M6 and M7 |
The gm/ID methodology uses transconductance efficiency (gm/ID, units V⁻¹) as the primary design variable instead of overdrive voltage VOV. It works across all inversion levels without approximation and naturally handles short-channel effects.
| Region | gm/ID (V⁻¹) | Inversion | Optimised For | Trade-off |
|---|---|---|---|---|
| Sub-threshold (WI) | 20 – 28 | Weak | Ultra-low power, max current efficiency | Slow speed, exponential IDS sensitivity |
| Moderate (MI) | 10 – 20 | Moderate | Best power-bandwidth product (sweet spot) | Complex modelling region |
| Saturation (SI) | 5 – 10 | Strong | High speed, good matching, predictable | Higher IDS required for given gm |
| Deep saturation | 1 – 5 | Very Strong | RF, maximum gm per area | Lowest current efficiency, self-heating risk |
Key relations: gm/ID = gm/IDS · gm·rds = gm/gds (intrinsic gain) · fT = gm/(2π·Cgg) · ID/W (current density, µA/µm). For a sizing target with given gm, W = gm / (gm/ID × ID/W).
| Corner | NMOS | PMOS | IDS vs TT | Typical Use |
|---|---|---|---|---|
| TT (this tool) | Typical | Typical | Nominal | Nominal characterisation, bias point design |
| FF | Fast | Fast | Higher | Speed check, timing closure |
| SS | Slow | Slow | Lower | Minimum gain/bandwidth check |
| FS | Fast | Slow | — | NMOS-dominated path worst case |
| SF | Slow | Fast | — | PMOS-dominated path worst case |
All data shown is TT corner, T = 27°C, VDS = VDD/2 (0.6V LV, 1.65V HV), VSB = 0. Temperature range for device operation: −40°C to +125°C. Simulation requires ngspice ≥ 38 with the PSP 103 model patch. Model files: sg13g2_lv_nmos.lib, sg13g2_lv_pmos.lib, sg13g2_hv_nmos.lib, sg13g2_hv_pmos.lib.
*.lib files. Vth0 values listed are from process control measurements and may differ from PSP model extraction.PMOS data is plotted using the absolute value convention: all quantities are converted to positive values for direct comparison with NMOS. Specifically: VGS → |VGS|, Vth → |Vth|, IDS → |IDS|, gm → |gm|. Overdrive voltage VOV = |VGS| − |Vth|, which is negative in sub-threshold and positive in inversion — same sign as NMOS.
In ngspice simulation, PMOS nodes are: drain=negative-rail, source=positive-rail, gate biased from positive-rail. The |VGS| convention means VGS sweeps from 0 to |VDD| in the characterisation script. All gm/ID curves are directly comparable between NMOS and PMOS after this normalisation.
Each gm/ID LUT file was generated by an ngspice DC sweep with the following key parameters:
| Parameter | LV (NMOS/PMOS) | HV (NMOS/PMOS) |
|---|---|---|
| W (width) | 2 µm | 2 µm |
| VDS | 0.6 V (VDD/2) | 1.65 V (VDD/2) |
| VSB | 0 V | 0 V |
| VGS sweep | 0.01 V → 1.65 V (16401 pts) | 0.01 V → 3.3 V (32901 pts) |
| Temperature | 27°C (300 K) | 27°C (300 K) |
| Process corner | TT | TT |
| Saved quantities | Vgs, gm, ID, Vth, gds, Cgg, Cgs, Cgd | Same |
Derived metrics: gm/ID = gm/IDS, gm/gds, ID/W = IDS/W_char [µA/µm], fT = gm/(2π·Cgg) [GHz], Cgd/Cgg, Cgs/Cgg. Downsampled to 300 points/curve for web delivery.
| Tool | Role | Version |
|---|---|---|
| ngspice | Circuit simulation (SPICE-compatible) | ≥ 38 with PSP103 patch |
| Xschem | Schematic entry, symbol library | ≥ 3.4.0 |
| Magic | Layout editor, DRC | ≥ 8.3.336 |
| KLayout | GDS viewer, DRC, LVS | ≥ 0.28.6 |
| netgen | LVS (layout vs schematic) | ≥ 1.5.254 |
| OpenEMS | EM simulation for RF passives | optional |
| IIC-OSIC-TOOLS | Docker image with all tools pre-installed | latest |
Contact IHP for fabrication: openpdk@ihp-microelectronics.com. The open-source PDK is released under Apache 2.0 (Copyright 2024 IHP PDK Authors).