GlobalFoundries GF180MCU — MOSFET Device Reference

The GF180MCU is a 0.18µm bulk CMOS process from GlobalFoundries, open-sourced in collaboration with Google. It targets 3.3V/5V/6V MCU and mixed-signal applications. All data below is sourced directly from the official PDK documentation at gf180mcu-pdk.rtfd.io.

Technology node 0.18µm bulk CMOS

Supply voltages 3.3V / 5V / 6V

SPICE model BSIM4 v4.5 / v4.6

License Apache 2.0

PDK source github.com/google/gf180mcu-pdk

Device Catalogue — All 9 MOSFET Flavours in This Repo

nfet_03v3 NMOS · 3.3V · SVT

Standard-Vt NMOS for 3.3V supply. This is the primary workhorse device for LV analog blocks — OTAs, comparators, current mirrors. BSIM4 v4.5 scalable model with full corner/statistical support. Minimum drawn gate L = 0.28µm (Lmin of 0.18µm process is technology-defined, not process Lmin).

Vdd nom

3.3 V

Vth₀ typ (W/L=10/0.28)

0.63 V

Idsat typ

510 µA/µm

Lmin drawn

0.28 µm

Wmin

0.22 µm

BVDSS typ

~9 V

pfet_03v3 PMOS · 3.3V · SVT

Complementary PMOS to nfet_03v3. Use for differential pairs, load devices, and cascode topologies. Has higher |Vth| than NMOS counterpart (~0.73V), lower mobility hence lower Idsat. Same gate oxide and supply rail. BSIM4 v4.5 with full corner support.

Vdd nom

3.3 V

Vth₀ typ

−0.73 V

Idsat typ

−250 µA/µm

Lmin drawn

0.28 µm

Wmin

0.22 µm

BVDSS typ

~8.5 V

nfet_03v3_dss NMOS · 3.3V · DSS/SAB

DSS = "Drain-Side Silicide Block" (also called SAB — Silicide Abatement Block). A silicide-blocking layer is placed over the drain to introduce a deliberate series resistance. This raises Vth, reduces Idsat slightly (~1%), but dramatically suppresses hot-carrier injection and impact ionisation — critical for long-lifetime precision analog and high-voltage sense paths. Subcircuit model wrapping nfet_03v3. DOP = 1.78µm, SOP = 0.48µm.

Vth₀ typ

0.63 V

Idsat typ

505 µA/µm

Idlin typ

57 µA/µm

DOP (drain SAB)

1.78 µm

SOP (source SAB)

0.48 µm

Key benefit

Low hot-carrier

pfet_03v3_dss PMOS · 3.3V · DSS/SAB

PMOS equivalent of nfet_03v3_dss. SAB inserted on the drain side of the channel to suppress hot-carrier degradation. Subcircuit model. Primarily used in precision low-leakage output stages or where PMOS long-term reliability is prioritised over Idsat performance. Slight Idsat reduction vs. plain pfet_03v3.

Vth₀ typ

−0.72 V

Idsat typ

−245 µA/µm

Idlin typ

−20 µA/µm

DOP (drain SAB)

1.78 µm

SOP (source SAB)

0.48 µm

Model type

Subcircuit

nfet_06v0 NMOS · 6V · SVT

Medium-voltage NMOS with thicker gate oxide for 6V supply operation. Higher Vth (~0.73V at L=0.7µm) due to thicker oxide. Used in power management, gate drivers, and any block exposed to a 5–6V supply rail. Minimum L = 0.6µm enforced by the thicker gate oxide. BSIM4 v4.5 with full corner/statistical support.

Vdd nom

6 V

Vth₀ typ (10/0.7)

0.73 V

Idsat typ @ 6V

570 µA/µm

Lmin drawn

0.6 µm

Wmin

0.3 µm

BVDSS typ

~11 V

pfet_06v0 PMOS · 6V · SVT

Medium-voltage PMOS for 6V operation. Higher |Vth| (~0.85V at L=0.55µm) vs. the 3.3V PMOS. Note Lmin is slightly different from the NMOS counterpart (0.55µm drawn minimum). Key device for MV differential pairs and 5V/6V supply cascode stages. BSIM4 v4.5.

Vdd nom

6 V

Vth₀ typ (10/0.55)

−0.85 V

Idsat typ @ 6V

−290 µA/µm

Lmin drawn

0.55 µm

Wmin

0.3 µm

BVDSS typ

~10.5 V

nfet_06v0_dss NMOS · 6V · DSS/SAB

6V NMOS with silicide-blocked drain. Larger SAB window than the 3.3V variant (DOP = 3.78µm, SOP = 0.28µm) reflecting the higher voltage stress. Critical for high-voltage hot-carrier reliability. Used in 5V–6V analog front-ends, ESD-sensitive input stages, and any precision MV current mirror. Subcircuit model wrapping nfet_06v0.

Vth₀ typ @ 6V

0.72 V

Idsat typ @ 5V

498 µA/µm

Idlin typ @ 5V

46 µA/µm

DOP (drain SAB)

3.78 µm

SOP (source SAB)

0.28 µm

Model type

Subcircuit

pfet_06v0_dss PMOS · 6V · DSS/SAB

6V PMOS with silicide-blocked drain (DOP = 2.78µm, SOP = 0.28µm). Suppresses hot-carrier degradation at elevated drain voltages. Subcircuit model. For 5–6V precision PMOS applications where device aging over operating lifetime matters — bandgap references, precision current sources in automotive/industrial designs.

Vth₀ typ @ 6V

−0.84 V

Idsat typ @ 5V

−233 µA/µm

Idlin typ @ 5V

−14 µA/µm

DOP (drain SAB)

2.78 µm

SOP (source SAB)

0.28 µm

Model type

Subcircuit

nfet_05v0_svt NMOS · 5V mode

This dataset uses the same nfet_06v0 physical device but characterised under 5V supply bias conditions (Vdd=5V for Idsat measurement). The 06v0 device can operate at either 5V or 6V depending on your supply — both corners are provided in the PDK. At 5V: Idsat typ ≈ 500 µA/µm, Vth₀ ≈ 0.70V (10/0.6). L range in this dataset: 0.75–5µm (18 points).

Vdd nom (this data)

5 V

Vth₀ typ (10/0.6)

0.70 V

Idsat typ @ 5V

500 µA/µm

L range (dataset)

0.75–5 µm

Physical device

nfet_06v0

BSIM version

4.5

What Is DSS / SAB?

🔴 DSS = Drain-Side Silicide Block · SAB = Silicide Abatement Block (same thing)

In standard CMOS, a metal silicide layer (TiSi₂, CoSi₂, or NiSi) is formed on source/drain and gate to reduce contact resistance. The _dss (or equivalently _sab) variant intentionally blocks silicidation on the drain side by depositing a dielectric mask before the silicide anneal step. This creates a deliberate, well-controlled series resistance in the drain diffusion region.

Why use it? At elevated Vds (especially in 6V devices), hot electrons injected into the gate oxide cause threshold voltage drift and transconductance degradation over time. The drain-side resistance drops part of the Vds before it reaches the pinch-off region, reducing peak lateral electric field and hot-carrier injection rate. This comes at the cost of slightly lower Idsat (~1%) and higher on-resistance.

The drain-side SAB overlap (DOP) is much larger than the source-side overlap (SOP) because hot carriers are generated at the drain end of the channel. For 3.3V devices: DOP = 1.78µm, SOP = 0.48µm. For 6V devices: DOP = 3.78µm (NMOS) / 2.78µm (PMOS), SOP = 0.28µm — the larger DOP accommodates the higher electric field at 6V.

Process Corner Guide (from PDK §2.4)

Typical–Typical. Nominal process parameters. Best estimate of silicon.

Fast NMOS + Fast PMOS. Low Vth, high Idsat. Bound extreme fast performance. Use for min-delay, max-power check.

Slow NMOS + Slow PMOS. High Vth, low Idsat. Bound worst-case delay and leakage.

Fast NMOS + Slow PMOS. N–P mismatch corner. Critical for pass-gate and CMOS logic static noise margins.

Slow NMOS + Fast PMOS. Opposite N–P mismatch. Tests latch-up susceptibility and complementary signal paths.

⚠ Note: These corners are primarily calibrated for predicting static logic delay, not analog operating points. For analog Monte Carlo, use the global+local statistical model (supported by all devices except nfet_06v0_nvt for local mismatch).

EP Electrical Specifications — Official PDK Numbers

nfet_03v3 · 3.3V NMOS (W/L = 10/0.28µm, 25°C)

Parameter	Slow (SS)	Typical	Fast (FF)	Unit
Vth₀ (max-Gm @ Vd=0.05V)	0.73	—	—	V
Vth₀ (max-Gm @ Vd=0.05V)	—	0.63	—	V
Vth₀ (max-Gm @ Vd=0.05V)	—	—	0.53	V
Idsat (Vds=Vgs=3.3V)	430	—	—	µA/µm
Idsat (Vds=Vgs=3.3V)	—	510	—	µA/µm
Idsat (Vds=Vgs=3.3V)	—	—	590	µA/µm
Ioff (Vds=3.63V, 25°C)	—	1	100	pA/µm
SubVt slope (max)	—	—	150	mV/dec
BVDSS (punch-through)	7	9	—	V

pfet_03v3 · 3.3V PMOS (W/L = 10/0.28µm, 25°C)

Parameter	Slow	Typical	Fast	Unit
\|Vth₀\|	0.85	—	—	V
\|Vth₀\|	—	0.73	—	V
\|Vth₀\|	—	—	0.61	V
\|Idsat\| (Vds=Vgs=−3.3V)	210	—	—	µA/µm
\|Idsat\| (Vds=Vgs=−3.3V)	—	250	—	µA/µm
\|Idsat\| (Vds=Vgs=−3.3V)	—	—	290	µA/µm
\|Ioff\| (Vds=3.63V, 25°C)	20	1	—	pA/µm
SubVt slope (max)	—	—	150	mV/dec
\|BVDSS\|	—	8.5	6.5	V

nfet_06v0 · 6V NMOS (W/L = 10/0.7µm, 25°C)

Parameter	Slow	Typical	Fast	Unit
Vth₀	0.85	—	—	V
Vth₀	—	0.73	—	V
Vth₀	—	—	0.61	V
Idsat (Vds=Vgs=6V)	480	—	—	µA/µm
Idsat (Vds=Vgs=6V)	—	570	—	µA/µm
Idsat (Vds=Vgs=6V)	—	—	660	µA/µm
Ioff (Vds=6.6V, 25°C)	—	1	10	pA/µm
SubVt slope (max)	—	—	150	mV/dec
BVDSS	8.5	11	—	V

pfet_06v0 · 6V PMOS (W/L = 10/0.55µm, 25°C)

Parameter	Slow	Typical	Fast	Unit
\|Vth₀\|	0.98	—	—	V
\|Vth₀\|	—	0.85	—	V
\|Vth₀\|	—	—	0.72	V
\|Idsat\| (Vds=Vgs=−6V)	240	—	—	µA/µm
\|Idsat\| (Vds=Vgs=−6V)	—	290	—	µA/µm
\|Idsat\| (Vds=Vgs=−6V)	—	—	340	µA/µm
Ioff (Vds=6.6V, 25°C)	10	1	—	pA/µm
\|BVDSS\|	—	10.5	8.5	V

nfet_03v3_dss · 3.3V NMOS SAB (W/L = 10/0.28µm)

Parameter	Slow	Typical	Fast	Unit
Vth₀	0.73	—	—	V
Vth₀	—	0.63	—	V
Vth₀	—	—	0.53	V
Idsat	426	—	—	µA/µm
Idsat	—	505	—	µA/µm
Idsat	—	—	586	µA/µm
Idlin (lin region)	52	—	—	µA/µm
Idlin (lin region)	—	57	—	µA/µm
Idlin (lin region)	—	—	63	µA/µm

nfet_06v0_dss · 6V NMOS SAB (W/L = 10/0.6µm, 5V bias)

Parameter	Slow	Typical	Fast	Unit
Vth₀	0.84	—	—	V
Vth₀	—	0.72	—	V
Vth₀	—	—	0.58	V
Idsat (@ 5V)	398	—	—	µA/µm
Idsat (@ 5V)	—	498	—	µA/µm
Idsat (@ 5V)	—	—	598	µA/µm
Idlin (lin @ 5V)	39	46	53	µA/µm

Instance Parameter Limits (Design Constraints)

Device	BSIM	W min (µm)	W max (µm)	L min (µm)	L max (µm)	nf min	Vdd nom
nfet_03v3	4.5	0.22	100	0.28	50	1	3.3V
pfet_03v3	4.5	0.22	50	0.28	100	1	3.3V
nfet_03v3_dss	4.5*	0.22	100	0.28	50	1	3.3V
pfet_03v3_dss	4.5*	0.22	50	0.28	100	1	3.3V
nfet_06v0	4.5	0.3	100	0.6	50	1	5V/6V
pfet_06v0	4.5	0.3	100	0.5	50	1	5V/6V
nfet_06v0_dss	4.5*	0.3	100	0.6	50	1	5V/6V
pfet_06v0_dss	4.5*	0.3	100	0.5	50	1	5V/6V

* DSS devices are subcircuit wrappers around the base SVT device; the BSIM model is the same. · Values from PDK §1.5.1.

Designer's Quick Reference

3.3V NMOS Vth range (SS→FF)

0.53 – 0.73 V

max-Gm method, Vd=0.05V

3.3V PMOS |Vth| range

0.61 – 0.85 V

~200mV window across corners

6V NMOS Vth range

0.61 – 0.85 V

Measured at Vd=0.05V

6V PMOS |Vth| range

0.72 – 0.98 V

~260mV window, larger than LV

SubVt slope (all devices)

≤ 150 mV/dec

Typ ~80–100 mV/dec at 25°C

Ioff (3.3V, 25°C)

1–100 pA/µm

Worst-case leakage spec (NMOS)

3.3V Idsat spread (NMOS)

±16% from typical

430–590 µA/µm

6V Idsat spread (NMOS)

±16% from typical

480–660 µA/µm at 6V

Measurement bias for Vth

Vd = 0.05V

max-Gm method (Vth₀ not Vth₁)

BVDSS headroom (3.3V)

7–9 V

≥2× supply — good for ESD

BVDSS headroom (6V)

8.5–11 V

≥1.4× supply

Extraction geometry set

W=0.22–100µm, L=0.28–3µm

Actual measured devices for BSIM fitting

📚 Source: PDK §2.5 · Electrical Specs §1.0–§7.0 · Device List §1.4.1 · All data at 25°C unless stated. Vth₀ uses max-Gm extraction.